Texas Instruments LMK05318 Network Synchronizer Clock with BAW
Texas Instruments LMK05318 Network Synchronizer Clock with BAW provides jitter cleaning, clock generation, advanced clock monitoring, and superior hitless switching performance. These features are designed to meet the stringent timing requirements of communications infrastructure and industrial applications. The device's ultra-low jitter and high power supply noise rejection (PSNR) can reduce bit error rates (BER) in high-speed serial links. The device can generate output clocks with a 50fs RMS jitter using TI's proprietary Bulk Acoustic Wave (BAW) VCO technology, independent of the jitter and frequency of the XO and reference inputs.
The DPLL supports programmable loop bandwidth for jitter and wander attenuation, while the two APLLs support fractional frequency translation for flexible clock generation. The synchronization options supported on the DPLL include hitless switching, digital holdover, and DCO mode with less than 0.001ppb frequency step size for precision clock steering (IEEE 1588 PTP slave). The DPLL can phase-lock to a 1PPS (pulse-per-second) reference input and support optional zero-delay mode on one output to achieve deterministic input-to-output phase alignment with programmable offset. The advanced reference input monitoring block ensures robust clock fault detection and helps to minimize output clock disturbance when a loss of reference (LOR) occurs.
Features
- One Digital Phase-Locked Loop (DPLL) with
- ±50ps phase transient hitless switching
- Programmable loop bandwidth with fast lock
- Standards-compliant synchronization and holdover using a low-cost TCXO/OCXO
- Two Analog Phase-Locked Loops (APLLs) with industry-leading jitter performance
- 50fs RMS jitter at 312.5MHz (APLL1)
- 125fs RMS jitter at 155.52MHz (APLL2)
- Two reference clock inputs
- Priority-based input selection
- Digital holdover on the loss of reference
- Eight clock outputs with programmable drivers
- Up to six different output frequencies
- AC-LVDS, AC-CML, AC-LVPECL, HCSL, and 1.8V LVCMOS output formats
- EEPROM / ROM for custom clocks on power-up
- Flexible configuration options
- 1Hz (1PPS) to 800MHz on input and output
- 10 to 100MHz XO/TCXO/OCXO input
- < 0.001ppb/Step for precise clock steering (IEEE 1588 PTP slave) DCO mode
- Advanced clock monitoring and status
- I2C or SPI interface
- –83dBc (50mVpp noise on 3.3V supply) PSNR
- 3.3V supply with 1.8V, 2.5V, or 3.3V outputs
- –40°C to +85°C industrial temperature range
Applications
- SyncE (G.8262), SONET/SDH (Stratum 3/3E, G.813, GR-1244, GR-253), IEEE 1588 PTP slave clock, or optical transport network (G.709)
- 400G line cards, fabric cards for Ethernet switches and routers
- Wireless Base Station (BTS), wireless backhaul
- Test and measurement, medical imaging
- Jitter cleaning, wander attenuation, and reference clock generation for 56G/112G PAM-4 PHYs, ASICs, FPGAs, SoCs, and processors
Functional Block Diagram
Associated Products
Texas Instruments Công nghệ sóng âm gộp (BAW)
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