DS90CR286AT-Q1 LVDS Receiver

Texas Instruments DS90CR286AT-Q1 LVDS Receiver converts four LVDS (Low Voltage Differential Signaling) data streams back into parallel 28 bits of LVCMOS data. The receiver data outputs strobe on the output clock's rising edge. The receiver LVDS clock operates at rates from 20 to 66MHz. The DS90CR286AT-Q1 phase-locks to the input LVDS clock, samples the serial bit streams at the LVDS data lines, and converts them into 28-bit parallel output data. At an incoming clock rate of 66MHz, each LVDS input line is running at a bit rate of 462Mbps. This results in a maximum throughput of 1.848Gbps. The DS90CR286AT-Q1 device is enhanced over prior generation receivers due to a wider data valid time on the receiver output.