Analog Devices Inc. ADF4382x Fractional-N Phased-Locked Loops (PLLs)
Analog Devices ADF4382x Fractional-N Phased-Locked Loop (PLL) is a high-performance, ultra-low jitter, fractional-N phased-locked loop (PLL). It has an integrated voltage-controlled oscillator (VCO) ideally suited for the local oscillator (LO) generation for 5G or data converter clock applications. The high-performance PLL has a figure of merit of -239dBc/Hz, low 1/f noise, and a high PFD frequency of 625MHz in integer mode that can achieve ultra-low in-band noise and integrated jitter. The ADF4382x can generate frequencies in a fundamental octave range of 11.5GHz to 21GHz, eliminating the need for subharmonic filters. The divide by two and four output dividers on the ADF4382x allow frequencies to be generated from 5.75GHz to 10.5GHz and 2.875GHz to 5.25GHz, respectively.
The Analog Devices ADF4382x automatically aligns its output to the input reference edge for multiple data converter clock applications by including the output divider in the PLL feedback loop. A programmable reference to output delay with <1ps resolution is provided for applications requiring deterministic delay or delay adjustment capability. The reference to output delay matching across multiple devices and over temperature allows predictable and precise multichip clock and system reference (SYSREF) alignment. The simplicity of the ADF4382x block diagram eases development time with a simplified serial peripheral interface (SPI) register map, repeatable multichip clock alignment, and limiting unwanted clock spurs by allowing off-chip SYSREF generation.
Features
- 687.5MHz to 22GHz output frequency range
- Integrated RMS jitter at 20GHz
- 20fs (integration bandwidth: 100Hz to 100MHz)
- 31fs (ADC SNR method)
- Fast <1μs VCO calibration time
- <100μs VCO autocalibration time
- Phase noise floor of -156dBc/Hz at 20GHz
- PLL specifications
- -239dBc/Hz normalized in-band phase noise floor
- -287dBc/Hz normalized 1/f phase noise floor
- 625MHz maximum phase/frequency detector input frequency
- 4.5GHz reference input frequency
- -90dBc typical spurious fPFD
- Reference to output delay specifications
- 0.06ps/°C propagation delay temperature coefficient
- <1ps adjustment step size
- Multichip output phase alignment
- 3.3V and 5V power supplies
- ADIsimPLL™ loop filter design tool support
- 7mm × 7mm, 48-terminal LGA package
- -40°C to +105°C operating temperature range
Applications
- High-performance data converter clocking
- Wireless infrastructure (MC-GSM, 5G, 6G)
- Test and measurement
Functional Block Diagram
Development Tool
Analog Devices Inc. EV-ADF4382A Evaluation Board
Designed to evaluate and demonstrate the ADF4382A frequency synthesizer with integrated VCO.