Lattice Semiconductor ECP5 Family FPGAs
Lattice Semiconductor ECP5 Family FPGAs are optimized to deliver high-performance features like an enhanced DSP architecture, high-speed SERDES, and high-speed source-synchronous interfaces in an economical FPGA fabric. This combination is achieved through advances in device architecture and the use of 40nm technology making the devices suitable for high-volume, high-speed, low-cost applications. The ECP5 device family covers look-up-table (LUT) capacity to 84K logic elements and supports up to 365 users I/Os. The ECP5 device family also offers up to 156 18x18 multipliers and a wide range of parallel I/O standards.
The Lattice Semiconductor ECP5 FPGAs are available in a 144-lead TQFP (Thin Quad Flat Pack) package and in 256-, 285-, 381-, 554-, and 756-ball caBGA (ChipArray® Ball Grid Array) packages.
Features
- Higher logic density for increased system integration
- 24K to 84K LUTs
- 197 to 365 user-programmable I/Os
- Embedded SERDES
- 270Mbps to 3.2Gbps for Generic 8b10b, 10-bit SERDES, and 8-bit SERDES modes
- Data rates 270Mbps to 3.2Gbps per channel for all other protocols
- Up to four channels per device: PCI Express, Ethernet (1GbE, SGMII, XAUI), and CPRI
- sysDSP™
- Fully cascadable slice architecture
- 12 to 160 slices for high performance multiply and accumulate
- Powerful 54-bit ALU operations
- Time Division Multiplexing MAC Sharing
- Rounding and truncation
- Each slice supports — Half 36x36, two 18x18 or four 9x9 multipliers — Advanced 18x36 MAC and 18x18 Multiply-Multiply-Accumulate (MMAC) operations
- Pre-Engineered Source Synchronous I/O
- DDR registers in I/O cells
- Dedicated read/write leveling functionality
- Dedicated gearing logic
- Source synchronous standards support — ADC/DAC, 7:1 LVDS, XGMII — high-speed ADC/DAC devices
- Dedicated DDR2/DDR3 and LPDDR2/LPDDR3 memory support with DQS logic, up to 800Mbps data-rate
- Flexible memory resources
- Up to 3.744Mbits sysMEM™ Embedded Block RAM (EBR)
- 194K to 669K bits distributed RAM
- sysCLOCK analog PLLs and DLLs
- Four DLLs and four PLLs in LFE5-45 and LFE5- 85; two DLLs and two PLLs in LFE5-25
- Programmable sysI/O™ buffer supports a wide range of interfaces
- On-chip termination
- LVTTL and LVCMOS 33/25/18/15/12
- SSTL 18/15 I, II
- HSUL12
- LVDS, Bus-LVDS, LVPECL, RSDS, MLVDS
- subLVDS and SLVS, MIPI D-PHY input interfaces
- Flexible device configuration
- Shared bank for configuration I/Os
- SPI boot Flash interface
- Dual-boot images supported
- Slave SPI
- TransFR™ I/O for simple field updates
- Single Event Upset (SEU) mitigation support
- Soft Error Detect - Embedded hard macro
- Soft Error Correction - without stopping user operation
- Soft Error Injection - emulate SEU event to debug system error handling
- System-level support
- IEEE 1149.1 and IEEE 1532 compliant
- Reveal Logic Analyzer
- On-chip oscillator for initialization and general use
- 1.1V core power supply
Development Tools
Lattice Semiconductor ECP5 Evaluation Board
Allows users to investigate and experiment with the features of ECP5-5G FPGA.
Lime Microsystems LimeSDR Mini 2.0
Open-source USB stick SDR based on the LMS7002M RF Transceiver and the Lattice ECP5 FPGA.
Đã phát hành: 2015-09-14
| Đã cập nhật: 2022-07-20