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Lattice Semiconductor XP2 Non-Volatile Field Programmable Gate Arrays

Lattice's LatticeXP2 non-volatile field programmable gate arrays combine a look-up table-based FPGA fabric with Flash non-volatile cells in a flexiFlash™ architecture. The flexiFlash architecture provides instant-on, small footprint, on-chip storage with FlashBAK™ embedded block memories, Serial TAG memory, and design security. The devices include LUT-based logic, distributed and embedded memory, Phase Locked Loops, pre-engineered source synchronous I/O, and enhanced sysDSP blocks. The product is ideal for high-volume and low-cost applications.

Features

  • flexiFLASH™ Architecture
    • Instant-on
    • Infinitely reconfigurable
    • Single-chip
    • FlashBAK™ technology
    • Serial TAG memory
    • Design security
  • Live Update Technology
    • TransFR™ technology
    • Secure updates with 128 bit AES encryption
    • Dual-boot with external SPI
  • sysDSP™ Block
    • Three to eight blocks for high performance
  • Multiply and Accumulate
    • 12 to 32 18x18 multipliers
    • Each block supports one 36x36 multiplier or four 18x18 or eight 9x9 multipliers
  • Embedded and Distributed Memory
    • Up to 885 Kbits sysMEM™ EBR
    • Up to 83 Kbits Distributed RAM
  • sysCLOCK™ PLLs
    • Up to four analog PLLs per device
    • Clock multiply, divide and phase shifting
  • Flexible I/O Buffer
    • sysIO™ buffer supports:
      • LVCMOS 33/25/18/15/12; LVTTL
      • SSTL 33/25/18 class I, II
      • HSTL15 class I; HSTL18 class I, II
      • PCI
      • LVDS, Bus-LVDS, MLVDS, LVPECL, RSDS
  • Pre-engineered Source Synchronous Interfaces
    • DDR / DDR2 interfaces up to 200 MHz
    • 7:1 LVDS interfaces support display applications
    • XGMII
  • Density And Package Options
    • 5k to 40k LUT4s, 86 to 540 I/Os
    • csBGA, TQFP, PQFP, ftBGA and fpBGA packages
    • Density migration supported
  • Flexible Device Configuration
    • SPI (master and slave) Boot Flash Interface
    • Dual Boot Image supported
    • Soft Error Detect (SED) macro embedded
  • System-Level Support
    • IEEE 1149.1 and IEEE 1532 Compliant
    • On-chip oscillator for initialization & general use
    • Devices operate with 1.2V power supply

Block Diagram

Lattice Semiconductor XP2 Non-Volatile Field Programmable Gate Arrays
Đã phát hành: 2008-06-25 | Đã cập nhật: 2022-03-11