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Texas Instruments CDCU877 Phase-Lock Loop Clock Driver

Texas Instruments CDCU877 Phase-Lock Loop Clock Driver is a high-performance, low-jitter, low-skew, zero-delay buffer. It distributes a differential clock input pair (CK, /CK) to 10 differential pairs of clock outputs (Yn, /Yn) and one differential pair of feedback clock outputs (FBOUT, /FBOUT). The clock outputs are controlled by the input clocks (CK, /CK), the feedback clocks (FBIN, /FBIN), the LVCMOS control pins (OE, OS), and the analog power input (AVDD). When OE is low, the clock outputs, except FBOUT, /FBOUT, are disabled while the internal PLL maintains its locked-in frequency. OS (output select) is a program pin that must be tied to GND or VDD. When OS is high, OE functions as previously described. When OS and OE are both low, OE does not affect Y7, /Y7, as these are free-running. When AVDD is grounded, the PLL is turned off and bypassed for test purposes.

When both clock inputs (CK, /CK) are logic low, the device enters a low power mode. An input logic detection circuit on the differential inputs, independent from input buffers, detects the logic at a low level and performs in a low power state where all outputs, the feedback, and the PLL are off. When the clock inputs transition from logic low to differential signals, the PLL turns back on. The inputs and the outputs are then enabled, and the PLL obtains phase lock between the feedback clock pair (FBIN, /FBIN) and the clock input pair (CK, /CK) within the specified stabilization time. The Texas Instruments CDCU877 can track spread spectrum clocking (SSC) for reduced EMI. This device operates from 0°C to 70°C.

Features

  • 1.8V Phase Lock Loop clock driver for Double Data Rate (DDR II) applications
  • Spread spectrum clock compatible
  • 10MHz to 400MHz operating frequency
  • < 135mA low current consumption
  • ±30ps low jitter (Cycle-Cycle)
  • 35ps low output skew
  • ±20ps low period jitter
  • ±15ps low dynamic phase offset
  • ±50ps low static phase offset
  • Distributes one differential clock input to ten differential outputs
  • 52-Ball µBGA (MicroStar™ Junior BGA, 0.65mm pitch) and 40-pin MLF
  • External feedback pins (FBIN, FBIN) are used to synchronize the outputs to the input clocks
  • Meets or exceeds JESD82-8 PLL standard for PC2-3200/4300
  • Fail-safe inputs

Logic Diagram

Schematic - Texas Instruments CDCU877 Phase-Lock Loop Clock Driver
Đã phát hành: 2020-12-18 | Đã cập nhật: 2024-10-22