Texas Instruments SN74SSTUB32864 25-Bit Configurable Register Buffer
Texas Instruments SN74SSTUB32864 25-Bit Configurable Register Buffer is designed for 1.7V to 1.9V VCC operation. In the 1:1 pinout configuration, only one device per DIMM is required to drive nine SDRAM loads. In the 1:2 pinout configuration, two devices per DIMM are required to drive eighteen SDRAM loads. All inputs are SSTL_18, except the reset (RESET) and control (Cn) inputs, which are LVCMOS. All outputs are edge-controlled circuits optimized for unterminated DIMM loads and meet SSTL_18 specifications.
The Texas Instruments SN74SSTUB32864 operates from a differential clock (CLK and CLK). The data is registered at the crossing of CLK going high and CLK going low. The C0 input controls the pinout configuration of the 1:2 pinout from register-A configuration (when low) to register-B configuration (when high). The C1 input controls the pinout configuration from 25-bit 1:1 (when low) to 14-bit 1:2 (when high). C0 and C1 should not be switched during normal operation. The controls should be hard-wired to a valid low or high level to configure the register in the desired mode. In the 25-bit 1:1 pinout configuration, the A6, D6, and H6 terminals are driven low and are do-not-use (DNU) pins.
In the DDR2 RDIMM application, RESET is specified to be completely asynchronous to CLK and CLK. Therefore, no timing relationship can be ensured between the two. When entering reset, the register is cleared, and the data outputs are driven low quickly, relative to the time required to disable the differential input receivers. However, when coming out of reset, the register becomes active quickly, relative to the time required to enable the differential input receivers. As long as the data inputs are low, and the clock is stable during the time from the low-to-high transition of RESET until the input receivers are fully enabled, the design of the SN74SSTUB32864 ensures that the outputs remain low, thus ensuring there will be no glitches on the output.
Features
- Member of the Texas Instruments Widebus+™ family
- Pinout optimizes DDR2 DIMM PCB layout
- Configurable as 25-Bit 1:1 or 14-Bit 1:2 registered buffer
- Chip-select inputs gate the data outputs from changing state and minimizes system power consumption
- Output edge-control circuitry minimizes switching noise in an unterminated line
- Supports SSTL_18 data inputs
- Differential clock (CLK and CLK) inputs
- Supports LVCMOS switching levels on the control and RESET inputs
- Supports industrial temperature range (-40°C to 85°C)
- RESET input disables differential input receivers, resets all registers, and forces all outputs low