Lattice Semiconductor Avant™-X High-Speed Mid-Range FPGAs - Coming Soon
Lattice Semiconductor Avant™-X High-Speed Mid-Range FPGAs offer performance with up to 637k System Logic Cells and up to 28x, 25G SerDes channels. These FPGAs are built on the Lattice Avant platform, ensuring low power consumption. The devices also feature modernized mid-range FPGA capabilities like advanced user security and support for DDR4/LPDDR4 and DDR5 memories.
The Lattice Avant-X FPGAs are ideal for efficient edge AI processing with fast and flexible SerDes supporting protocols like PCIe Gen 4 and 25G Ethernet. The FPGAs also have fast external memory support for LPDDR4/DDR4 up to 2400Mbps and DDR5 up to 2100Mbps, and up to 2.5x lower power consumption than competitors. With up to 7200 INT8 multipliers and 35.6Mb embedded memory, the devices implement AI/ML algorithms and high-speed interface packet buffering with remarkable efficiency.
Features
- Up to 28x SERDES channels operating up to 25Gbps
- Support up to PCI Gen4 8x with hardened link layer
- Support up to 25x Gbps Ethernet
- FPGA Fabric
- Up to 637k System Logic Cells
- 35.6Mb embedded memory
- 1800x – 18 x 18 multipliers (fracture to 7200x – 8 x 8 multipliers)
- 600+ System Logic Cells (SLCs) boot time <60ms
- Memory Support
- DDR4 / LPDDR4 supports up to 2400Mbps
- DDR5 support up to 2100Mbps
- Security
- Class-leading bitstream encryption and authentication
- Advanced user security functions
Industrial Networking NIC
• Flexible industrial Ethernet and field Bus interfaces up to 25G per port for cameras/high BW machine data
• RISC-V CPU and Lattice Propel System design tools HW
• Low latency, deterministic switching and control processing, protocol acceleration
• DMA into host/industrial computer for processing
Machine Vision
• Sensor interface - MIPI CSI-2, LVDS
• Customizable ISP for image processing
• Lattice sensAI Artificial Intelligence for object/defect detection
• High BW 25GbE connectivity enables streaming uncompressed/lossless quality video
Packet Processing and Board Control
• Bridge CPU via PCIe to multiple control plane peripherals (I2C, UART, GPIO), board management functions, and up to 25GE control plane traffic
• Security functions (e.g., encryption, authentication) implemented in FPGA help secure control plane traffic
• 25G SerDes supporting PCIe Gen 4 x4 (in hard IP) and 25 Gigabit Ethernet
• Fast FPGA configuration supports board management needs and PCIe boot-time requirements
Videos
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